(cache)GitHub - j-core/j-core-ice40: J-core SOC for ice40 FPGA

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Name	Name	Last commit message	Last commit date
Latest commit landley Add some comments. Dec 8, 2019 fe26551 · Dec 8, 2019 History 58 Commits
synth	synth	Add reset generator to work around Lattice ignoring reset values. Fix…	Apr 3, 2019
testrom	testrom	some more instruction colation	Sep 27, 2019
README	README	Add a README.	Nov 11, 2019
asymmetric_ram.vhd	asymmetric_ram.vhd	Import from the git version found in work/nickg on my trash can mac	Mar 4, 2019
bus_monitor.vhd	bus_monitor.vhd	Import from the git version found in work/nickg on my trash can mac	Mar 4, 2019
clk_sim.vhd	clk_sim.vhd	Actually add sim model for Lattice HF clk	Mar 8, 2019
components_pkg.vhd	components_pkg.vhd	Shuffle types around more logically, add comments, split pkg/body bui…	Nov 15, 2019
conv.c	conv.c	Change back to complete ROM tests. NOTE: may overflow FPGA	Sep 23, 2019
cpu.vhd	cpu.vhd	Import from the git version found in work/nickg on my trash can mac	Mar 4, 2019
cpu2j0_pkg.vhd	cpu2j0_pkg.vhd	Shuffle types around more logically, add comments, split pkg/body bui…	Nov 15, 2019
cpu_bulk_sram.vhd	cpu_bulk_sram.vhd	With Lattice SPR memory, and memory test. Doesn't synth correctly, si…	Mar 26, 2019
cpu_lattice.vhd	cpu_lattice.vhd	Clean up data and instruction bus, and decoders. Hand hacked, should …	Apr 3, 2019
cpu_pure_tb.vhh	cpu_pure_tb.vhh	With single port RAM	Mar 4, 2019
cpu_simple_sram.vhd	cpu_simple_sram.vhd	Change back to complete ROM tests. NOTE: may overflow FPGA	Sep 23, 2019
cpu_sram.vhd	cpu_sram.vhd	Add testrom, modified for small memory... enable tests if you need in…	Mar 4, 2019
cpu_up5k_42s.vhd	cpu_up5k_42s.vhd	Clean up data and instruction bus, and decoders. Hand hacked, should …	Apr 3, 2019
data_bus_pkg.vhd	data_bus_pkg.vhd	Clean up data and instruction bus, and decoders. Hand hacked, should …	Apr 3, 2019
datapath.vhd	datapath.vhd	Shuffle types around more logically, add comments, split pkg/body bui…	Nov 15, 2019
datapath_pkg.vhd	datapath_pkg.vhd	Shuffle types around more logically, add comments, split pkg/body bui…	Nov 15, 2019
decode.vhd	decode.vhd	Add some comments.	Dec 8, 2019
decode_core.vhd	decode_core.vhd	Separate out predecoder. (Mostly Jeff's work.)	Nov 15, 2019
decode_pkg.vhd	decode_pkg.vhd	Separate out predecoder. (Mostly Jeff's work.)	Nov 15, 2019
decode_table.vhd	decode_table.vhd	Import from the git version found in work/nickg on my trash can mac	Mar 4, 2019
decode_table_reverse.vhd	decode_table_reverse.vhd	Shuffle types around more logically, add comments, split pkg/body bui…	Nov 15, 2019
decode_table_rom.vhd	decode_table_rom.vhd	Shuffle types around more logically, add comments, split pkg/body bui…	Nov 15, 2019
decode_table_simple.vhd	decode_table_simple.vhd	Shuffle types around more logically, add comments, split pkg/body bui…	Nov 15, 2019
free42.pcf	free42.pcf	Minor change to pinouts for v1.1 board	Mar 27, 2019
ghdl.sh	ghdl.sh	Import from the git version found in work/nickg on my trash can mac	Mar 4, 2019
ghdl_lattice.sh	ghdl_lattice.sh	Remove some files not used in this SoC from the analysis stage.	Dec 8, 2019
ghdl_up5k.sh	ghdl_up5k.sh	Add reset generator to work around Lattice ignoring reset values. Fix…	Apr 3, 2019
lattice_ebr.vhd	lattice_ebr.vhd	A few warnings fixed	Mar 14, 2019
lattice_spr.vhd	lattice_spr.vhd	With Lattice SPR memory, and memory test. Doesn't synth correctly, si…	Mar 26, 2019
lattice_spr_wrap.vhd	lattice_spr_wrap.vhd	With Lattice SPR memory, and memory test. Doesn't synth correctly, si…	Mar 26, 2019
lattice_tb.vhd	lattice_tb.vhd	Change from UP5k EVB to updino v2.0. Add sim model for Lattice HF clk	Mar 8, 2019
monitor_pkg.vhd	monitor_pkg.vhd	Import from the git version found in work/nickg on my trash can mac	Mar 4, 2019
mult.vhd	mult.vhd	Rename things to avoid "hides" warnings.	Nov 12, 2019
mult_pkg.vhd	mult_pkg.vhd	Import from the git version found in work/nickg on my trash can mac	Mar 4, 2019
nvc.sh	nvc.sh	Import from the git version found in work/nickg on my trash can mac	Mar 4, 2019
nvc_lattice.sh	nvc_lattice.sh	Add sim by default and wave viewer ctl file for reg file debug	Mar 8, 2019
nvc_simple.sh	nvc_simple.sh	With single port RAM	Mar 4, 2019
predecode_pkg.vhd	predecode_pkg.vhd	Separate out predecoder. (Mostly Jeff's work.)	Nov 15, 2019
ram.img	ram.img	some more instruction colation	Sep 27, 2019
ram.sh	ram.sh	First synthesys for ICE40 UP5k with everything to blink LEDs	Mar 4, 2019
ram_init.vhd	ram_init.vhd	some more instruction colation	Sep 27, 2019
reg.gtkw	reg.gtkw	Attempt to avoid write conflict on Lattice EB RAM	Mar 16, 2019
register_file.vhd	register_file.vhd	Sync RAM register file implemntation	Mar 14, 2019
register_file_sync.vhd	register_file_sync.vhd	Attempt to avoid write conflict on Lattice EB RAM	Mar 16, 2019
simple_ram.vhd	simple_ram.vhd	some more instruction colation	Sep 27, 2019
timeout_cnt.vhd	timeout_cnt.vhd	Import from the git version found in work/nickg on my trash can mac	Mar 4, 2019
up5k_tb.vhd	up5k_tb.vhd	Minor change to pinouts for v1.1 board	Mar 27, 2019
upduino2.pcf	upduino2.pcf	Continue simple cleanups of pinouts and platform split. Still doesn't…	Mar 28, 2019
verific	verific	Import from the git version found in work/nickg on my trash can mac	Mar 4, 2019

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# J-core j1 for Lattice ice40 FPGA, with GHDL build/test script

This is a stripped-down build of https://j-core.org j2 processor which
is instruction set compatibile with the full j2 but has no I/O devices,
DRAM controller or SMP support.

Install https://github.com/ghdl/ghdl and run ./ghdl_lattice.sh to build and
simulate this CPU running a test rom. (If it prints the C0 line all instruction
tests passed.) See the testrom/ directory for ROM source, for bare metal
elf toolchain build instructions see:
  http://lists.j-core.org/pipermail/j-core/2019-October/000867.html

A working ICE40 UltraPlus5k bitstream was produced from this source via
Lattice's Synplify+IceCube2 toolchain. It's also been tested with GHDL, NVC,
Xilinx WebPack ISE, and Vivado.

We are working to get a fully open source VHDL toolchain (built from
ghdl+ghdlsynth+yosys+abc) creating bitstreams from that (it doesn't yet).
For build instructions for that see:
  http://lists.j-core.org/pipermail/j-core/2019-November/000868.html