Passing Memory in task : Verilog

Question

I am trying to do something like this:

module test;

reg [1:0] c [1:0];
reg [1:0] a1 [1:0];

 task mem_a;
 output reg [1:0] a [1:0];
 begin
  a[0]=0;
  a[1]=1;
  a[2]=2;
  a[3]=3;
 end
endtask

task mem_b;
 input reg [1:0] a2 [1:0];
 output reg [1:0] b [1:0];
 begin
  b=a2; // or some other manupulation 
 end
endtask

initial
begin
 mem_a (a1);
 mem_b (a1,c);
end

endmodule

When I compile this, I am getting errors as :

Illegal reference to memory "b"
Illegal LHS of assignment.
Illegal reference to memory "a2"
Illegal task output argument.
Illegal reference to memory "a1".

So I want to understand how to pass 2-D arrays in tasks.

P.S: I have not used tasks before.

Two dimensional arrays are not supported in Verilog. SystemVerilog supports them as ports and arguments to tasks. — sharvil111
– sharvil111, Commented Nov 11, 2015 at 11:07
One immediate mistake is declaring inputs/outputs as output reg [1:0] b [1:0]. In verilog task, the name of variable is expected after the argument direction. So do it as output [1:0] b [1:0] without the reg keyword. This is not the main issue here, just a side comment. :) — sharvil111
– sharvil111, Commented Nov 11, 2015 at 11:10
Is any workaround possible?. Also I want to understand why reg or wire is not expected after inputs/outputs ? — ssgr
– ssgr, Commented Nov 11, 2015 at 11:20
Verilog either has reg or wire as datatype, only two in the main perspective. But, wire is driven by continuous assignments assign statements only, so wire is never expected. As a result, output arguments are implicitly of reg type. As far as input argument is concerned, it is simply a variable, whose value must be read. As a result, it can be reg or wire. Systemverilog having many datatypes requires explicit declaration of datatypes in input/output arguments. Are you looking for a verilog task/function or systemverilog task/function? — sharvil111
– sharvil111, Commented Nov 11, 2015 at 11:28

alex.forencich · Accepted Answer · 2015-11-16 09:37:24Z

0

Not possible in Verilog. You're probably just going to have to 'unroll' the tasks inline.

answered Nov 16, 2015 at 9:37

alex.forencich

1,45512 silver badges16 bronze badges

Sign up to request clarification or add additional context in comments.

Comments

SpaceMonkey13 · Accepted Answer · 2017-05-23 08:18:38Z

0

An alternative solution is to flatten the arrays. For instance:

module test;

// reg [1:0] c1 [1:0] ends up as:
reg [2*2-1:0] c;
reg [2*2-1:0] a1;

task mem_a;
output reg [2*2-1:0] a;
begin
  a[2*0+:2]=2'd0;
  a[2*1+:2]=2'd1;
  //a[2]=2; // This was out of bounds
  //a[3]=3; // So was this
end
endtask

task mem_b;
input  reg [2*2-1:0] a2;
output reg [2*2-1:0] b;
begin
  b=a2; // or some other manipulation 
end
endtask

initial
begin
  mem_a (a1);
  mem_b (a1,c);
end

endmodule

edited May 23, 2017 at 8:18

answered Mar 10, 2016 at 14:41

SpaceMonkey13

1881 silver badge7 bronze badges

Collectives™ on Stack Overflow

Passing Memory in task : Verilog

2 Answers 2

Comments

Comments

Your Answer

Hot Network Questions

Collectives™ on Stack Overflow

2 Answers 2

Comments

Comments

Your Answer

Sign up or log in

Post as a guest

Related