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  • openlane-vhdl-build Public

    Build scripts for tools to build j-core ASIC.

    Shell 7 2 Updated May 22, 2026

  • jcore-j1-ghdl Public

    A simple design targeting iCE40 up5k with GHDL + Yosys.

    VHDL 8 4 Updated Jun 5, 2023

  • jcore-soc Public

    J-Core SoC Base Platfrom. Top level for FPGA platforms, pulls in CPU, BootROM and various IP blocks.

    VHDL 29 10 Other Updated Nov 24, 2020

  • jcore-cpu Public

    J-Core J2/J32 5 stage pipeline CPU core

    VHDL 63 16 Other Updated Nov 24, 2020

  • jcore-jx Public

    The J-Core Jx Platform board hardware.

    17 7 Updated Jun 21, 2020

  • gnss-baseband Public

    Baseband Receiver IP for GPS like DSSS signals

    VHDL 42 28 Other Updated May 19, 2020

  • bootrom Public

    BootROM for JCore J2 SoCs

    C 6 8 Other Updated May 19, 2020

  • TurtleAtmel Public

    Code for the Atmel micro-controller USB interface

    C 5 3 Updated Mar 24, 2020

  • j-core-ice40 Public

    J-core SOC for ice40 FPGA

    VHDL 20 3 Updated Dec 8, 2019